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LTC3220/LTC3220-1
OPERATION
Bus Write Operation
The master initiates communication with the LTC3220/
LTC3220-1 with a START condition and a 7-bit address
followed by the write bit R/W = 0. If the address matches
that of the LTC3220/LTC3220-1, the LTC3220/LTC3220-1
return an acknowledge. The master should then deliver the
most signi?cant sub-address byte for the data register to
be written. Again the LTC3220/LTC3220-1 acknowledge and
then the data is delivered starting with the most signi?cant
bit. This cycle is repeated until all of the required data reg-
isters have been written. Any number of data latches can be
written. Each data byte is transferred to an internal holding
latch upon the return of an acknowledge. After all data
bytes have been transferred to the LTC3220/LTC3220-1,
the master may terminate the communication with a STOP
condition. Alternatively, a Repeat-START condition can be
initiated by the master and another chip on theI 2 C bus can
be addressed. This cycle can continue inde?nitely and the
LTC3220/LTC3220-1 will remember the last input of valid
data that it received. Once all chips on the bus have been
addressed and sent valid data, a global STOP condition
can be sent and the LTC3220/LTC3220-1 will update all
registers with the data that it had received.
In certain circumstances the data on the I 2 C bus may be-
come corrupted. In these cases the LTC3220/LTC3220-1
respond appropriately by preserving only the last set of
complete data that it has received. For example, assume
the LTC3220/LTC3220-1 has been successfully addressed
and is receiving data when a STOP condition mistakenly
occurs. The LTC3220/LTC3220-1 will ignore this STOP
condition and will not respond until a new START condi-
tion, correct address, sub-address and new set of data
and STOP condition are transmitted.
Likewise, if the LTC3220/LTC3220-1 were previously ad-
dressed and sent valid data but not updated with a STOP,
they will respond to any STOP that appears on the bus with
only one exception, independent of the number of Repeat-
START’s that have occurred. If a Repeat-START is given
and the LTC3220/LTC3220-1 successfully acknowledge
their addresses and ?rst byte, they will not respond to a
STOP until all bytes of the new data have been received
and acknowledged.
Quick Write
Registers REG1 to REG18 can be written in parallel by set-
ting Bit 0 of REG 0 high. When this bit is set high the next
write sequence to REG1 will write the data to REG1 through
REG18, which are all of the universal LED registers.
32201fc
15
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